Analog to digital converters are judged on parameters such as sampling rate, noise, linearity, power consumption and resolution.
Each of these parameters can affect the choice of analog to digital converter (ADC) technology that is chosen for a task. For example “Flash converters” offer high throughput rates, but since each possible output result is evaluated by a respective comparator, then the comparator input referred offset limits the minimum bit size that can be resolved. Furthermore providing large numbers of comparators can be relatively power hungry.
Where noise performance is prioritized, then the noise shaping properties of sigma-delta (ΣΔ) converters may make them attractive. The ΣΔ converter uses a low resolution quantizer, often only 1 or 2 bits, to significantly oversample an input signal. This gives good linearity. Such circuits also provide the possibility to make the noise transfer function different from the signal transfer function. This gives the designer an option to move quantization noise away from the bandwidth of the signal. The conversion rates tends to lower than other ADC technologies.
Successive approximation register (SAR) analog to digital converters can be used to provide good resolution, good power consumption and reasonable noise performance at reasonable sampling rates. However there is a continuing need to improve ADC performance.